1. Field of the Invention
The present application relates generally to an improved data processing apparatus and method and more specifically to an apparatus and method for providing a data transfer optimized software cache for irregular memory references.
2. Background of the Invention
Many emerging computer architectures are deploying application specific processors to address acceleration of targeted applications. Frequently, such systems include novel memory hierarchies which can be hard coded an optimized to produce high performance. The Cell Broadband Engine (CBE) processor, available from International Business Machines Corporation of Armonk, N.Y., is one of the recent chip multiprocessor architectures with very specific features, such as its heterogeneous computing units and its memory model.
The CBE architecture comprises nine processing cores on a single chip. These nine processing cores include one 64-bit Power Processing Element (PPE core) and eight Synergistic Processing Elements (SPE cores) that use 18-bit addresses to access a 256K local store. The PPE core accesses system memory using a cache-coherent memory hierarchy. The SPE cores access system memory via a Direct Memory Access (DMA) engine connected to a high bandwidth bus, relying on software to explicitly initiate DMA requests for data transfer. The bus interface allows issuing asynchronous DMA transfer requests and provides synchronization calls to check or wait for previously issued DMA requests to complete.